Introduction
Bimonthly, started in 1957
Administrator
Shanxi Provincial Education Department
Sponsor
Taiyuan University of Technology
Publisher
Ed. Office of Journal of TYUT
Editor-in-Chief
SUN Hongbin
ISSN: 1007-9432
CN: 14-1220/N
Administrator
Shanxi Provincial Education Department
Sponsor
Taiyuan University of Technology
Publisher
Ed. Office of Journal of TYUT
Editor-in-Chief
SUN Hongbin
ISSN: 1007-9432
CN: 14-1220/N
location: home > paper >
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Design of an ASIC TRNG Using 0.35 μm CMOS Technology
DOI:
10.16355/j.cnki.issn1007-9432tyut.2019.06.020
Received:
Accepted:
| Corresponding author | Institute | |
| ZHANG Jianguo;WANG Yuncai | Key Laboratory of Advanced Transducers and Intelligent Control System, Ministry of Education; |
abstract:
A chaotic true random number generator based on hybrid Boolean network was proposed. The entropy source is composed of an 18-node autonomous Boolean network, which is used to generate Boolean chaotic with high amplitude(
～3 V) and large bandwidth(～780 MHz). The Boolean chaos is sampled and quantized by using a synchronous Boolean network, and finally a real random number with a real-time rate of 100 Mbps is generated. At the same time, the ASIC chip design of the true random data generator was completed. The chip adopts SMIC 0.35-μm 3.3 V CMOS standard process, and the core circuit area is 0.02 mm~2. Back-end simulation verification of the chip layout was performed using the Cadence Spectre simulator. The simulation results show that the chip can output a sequence of true random numbers satisfying the randomness detection standard at 100 MHz clock.
Keywords:
ASIC;boolean chaos;random number generator;random test;autonomous boolean network